4.1 Central Processing Unit (CPU) architecture

Von Neumann model for a computer system

• There is a processor — the central processing unit (CPU)

• The processor has direct access to memory

• The memory contains a “stored program” (which can be replaced by another at any time) and the data required by the program

• The stored program consists of individual instructions

• The processor executes instructions sequentially

Understanding of the purpose and role of registers

• Storage components that allow very short access times

• Each register has limited storage capacity

• Can be general purpose (e.g. accumulator) or special purpose (e.g. CIR)

General purpose register

The Accumulator (ACC)

• Stores a value at a single time

• To be used by the ALU for the execution of an instruction

Special purpose registers

Program Counter (PC)

• Stores the address

• of the next instruction to be fetched

Memory Address Register (MAR)

• Stores the next address to be fetched

• held in the Program Counter (PC)

• The data at this address is then fetched

Memory Data Register (MDR)

• Stores the data from the address pointed to by the MAR

• The data in it is copied to the Current Instruction Register (CIR)

Current Instruction Register (CIR)

• Stores the current instruction while it is being decoded and executed

Index Register (IX)

• Stores a value only for index addressing

Status Register (SR)

• Interpreted as independent bits/flags

• Each flag is set depending on an event

• Addition overflow/result of operation is zero etc.

• Overflow flag (V) is set to 1 if an arithmetic operation results in an OVERFLOW being produced

• Carry flag (C) is set to 1 if there is a CARRY following an addition operation

• Negative flag (N) is set to 1 if the result of a calculation yields a NEGATIVE value

• Zero flag (Z) is set to 1 if the result of an arithmetic or logic operation is ZERO

Purpose and roles of Arithmetic and Logic Unit (ALU), Control Unit (CU) and system clock, Immediate Access Store (IAS)

Arithmetic Logic Unit (ALU)

• Performs arithmetic operations

• and logical comparisons

Control Unit (CU)

• Sends and receive signals

• Synchronises operations

• to execute instructions

• E.g. input, output

System clock

• Synchronises processes

• Controls activities outside the processor

Immediate Access Store (IAS)

• The components that are directly addressable by the processor

How data are transferred between various components of the computer system using the address bus, data bus and control bus

• Address bus
  • Used to carry an address
  • Address is loaded on the bus from the MAR as directed by the CU
  • Address specifies a location in memory or an I/O component which is due to receive data or from which data is to be read
  • One-way, only be used to send an address to a memory controller or an I/O controller

• Data bus
  • Used to carry data
  • Can be an instruction, an address or a value
  • Two-way, can be carrying data to or from an I/O device

• Control bus
  • Two-way, transmits a signal from the control unit to or from any other system component
  • Major use is to carry timing signals for the system clock
  • Signals it can transfer: Interrupt, timing, read, write

How factors contribute to the performance of the computer system, including processor type and number of cores, the bus width, clock speed and cache memory

• Clock sends out a number of pulses in a given time interval

• Increasing clock speeds would increase the processing speed

• But overall performance does not necessarily increase

• Factors to be considered:
  1. Width of the address bus and data bus
  2. Overclocking: changing the clock speed by accessing the BIOS, however some problems might arise
     • execution of instructions outside design limits which leads to unsynchronised operations
     • serious overheating of the CPU leading to unreliable performance
  3. Use of cache memory
     • cache uses SRAM while DRAM is used for main memory
     • faster access times since no need for refreshing
  4. Number of cores
     • more cores can improve computer performance
     • alleviates the need to continually increase clock speeds
     • however CPU has to communicate with more cores which might reduce potential performance

How different ports provide connection to peripheral devices, including connection to Universal Serial Bus (USB), High Definition Multimedia Interface (HDMI) and Video Graphics Array (VGA)

• USB ports
  • the computer automatically detects that a device is present, due to a small change in the voltage level on the data signal wires
  • the device is automatically recognised, the appropriate device driver is loaded up so that computer and device can communicate effectively
  • if a new device is detected, the computer will look for the device driver which matches the device

• High-definition multimedia interface (HDMI)
  • allows output (both audio and visual) to an HDMI-enabled device
  • support high-definition signals
  • digital replacement for the older Video Graphics Array (VGA) analogue system
  • increases the bandwidth, making it possible to supply the necessary data for high quality sound and visual effects

• Video Graphics Array (VGA)
  • supports 640 * 480 pixel resolution and refresh rate up to 60 Hz

Describe the stages of the Fetch-Execute (F-E) cycle

Fetch

• Next instruction is fetched from the memory address currently stored in the program counter (PC) and stored in the current instruction register (CIR)

• PC is incremented so the next instruction can be processed

• Decoded so that each instruction can be interpreted in the next part of the cycle

Execute

• The processor passes the decoded instruction as a set of control signals to the appropriate components within the computer system

• Allows each instruction to be carried out in its logical sequence

For the whole F-E cycle:

1. The PC contains the address of the memory location of the next instruction which has to be fetched

2. This address is then copied from the PC to the MAR using the address bus

3. The instruction at the address contained in MAR are then copied temporarily into the MDR

4. The instruction of the MDR are then copied and placed into the CIR

5. The value in the PC is then incremented by one so that it now points to the next instruction which has to be fetched

6. The instruction is finally decoded and then executed by sending out signals via the control bus to the various components of the computer system

Using Register Transfer Notation: (fetch stage only)

MAR <- [PC]
PC <- [PC] + 1; MDR <- [[MAR]]
CIR <- [MDR]

Note: square brackets mean the data stored in the entity

[MAR] is the address stored in MAR

[[MAR]] is the data stored at the address stored in MAR

Show understanding of the purpose of interrupts, including possible causes of interrupts, applications of interrupts, use of an Interrupt Service Handling Routine (ISR), when interrupts are detected during the fetch-execute cycle and how interrupts are handled

Reasons for an interrupt to be generated includes:

• a hardware fault

• I/O request

• program/software error

• a timer signal

• user interaction

An interrupt is handled by the following steps:

• At the END of the fetch-execute cycle (F-E cycle) the processor checks for interrupts

• If an interrupt flag is set

• All contents of registers are saved

• PC loaded with address of interrupt service routine

• When servicing of interrupts complete, processor restores registers

• Processor continues with next F-E cycle

• Archive

  • The contents of the program counter and any other registers are stored somewhere safe in memory

  • The appropriate interrupt handler or Interrupt Service Routine (ISR) program is initiated by loading its start address into the program counter

  • When the ISR program has been executed there is an immediate check to see if further interrupts need handling

  • Further interrupts are dealt with by repeated execution of the ISR program

  • If there are no further interrupts, the safely stored contents of the registers are restored to the CPU and the originally running program is resumed

4.2 Assembly language

• The only language that the CPU recognises is machine code

• Machines code consists of a sequence of instructions

• An instruction contains an opcode (the action the CPU has to perform)

• An instruction may not have an operand but up to three operands (the data to be used by the CPU) are possible

• Different processors have different instruction sets associated with them

• Different processors will have comparable instructions for the same operations, but the coding of the instructions will be different

Relationship between assembly language and machine code

• A programmer might wish to write a program where the actions taken by the processor are directly controlled

• However writing a substantial program as a sequence of machine code instructions would take a very long time

• Solution is to use assembly language

• For each machine code instruction there is an equivalent assembly language instruction which comprises
  • a mnemonic (a symbolic abbreviation) for the opcode
  • a character representation for the operand

• The assembly code is translated into machine code before it can be executed by the processor, and the translation program is called an assembler

• The use of the assembler allows special features such as:
  • comments
  • symbolic name for constants
  • labels for addresses
  • macros
  • directives

Different stages of the assembly process for a two-pass assembler

Pass 1

• Read the assembly language program one line at a time.

• Ignore anything not required, such as comments.

• Allocate a memory address for the line of code.

• Check the opcode is in the instruction set.

• Add any new labels to the symbol table with the address, if known.

• Place address of labelled instruction in the symbol table.

Pass 2

• Read the assembly language program one line at a time.

• Generate object code, including opcode and operand, from the symbol table generated in Pass 1.

• Save or execute the program.

Trace an assembly program

A set of instructions are grouped: data movement, input and output of data, arithmetic operations, unconditional and conditional instructions and compare instructions

Different modes of addressing: immediate, direct, indirect, indexed, relative

4.3 Bit manipulation

Understand and perform binary shifts: logical, arithmetic and cyclic; left shift, right shift

A shift involves moving the bits stored in a register a given number of places within the register

• Logical shift
  • Bits shifted out of the register are replaced with zeros
  • E.g. 10101111 shifted left logically three places would become 01111000

• Arithmetic shift
  • The sign of the number is preserved
  • E.g. 10101111 shifted right arithmetically three places would become 11110101 (basically cyclic shift but the sign bit is preserved)

• Cyclic shift
  • No bits are lost during a shift
  • Bits shifted out of one end of the register are introduced at the other end of the register

• Left shift
  • Bits shifted to the left, gives the direction for the above shifts only

• Right shift
  • Bits shifted to the right, gives the direction for the above shifts only

How bit manipulation can be used to monitor/control a device

• In monitoring and control, each bit in a register or memory location can be used as a flag and would need to be tested, set or cleared separately

• AND is used to check if the bit has been set, OR is used to set the bit and XOR is used to clear a bit that has been set